튜토리얼
고속신호 시스템의 신호무결성 및 전원무결성 문제와 분석 솔루션
박유순, 매니저
- 태성에스엔이 EBU HF팀
Abstract
Semiconductors have steadily increased their operating speed and integration density while the operating voltage has decreased from the past until now. This has caused various problems such as SI (Signal Integrity), PI (Power Integrity), EMI/EMC (Electro Magnetic Interference/Electro Magnetic Compatibility). In this tutorial, we introduce various SI/PI/EMI/EMC problem cases and how to analyze them. This tutorial explains how parasitic elements change depending on the design of transmission lines through analysis of the relationship between S-parameters and characteristic impedance, and the relationship between characteristic impedance and parasitic components. This tutorial introduces how the resonant frequency, determined by the size and shape of the PCB, affects the product and how to solve EMI issues that may arise.
Yusoon Park currently works at TAE SUNG S&E, Inc. as an Ansys simulation expert. He received his bachelor's degree in Electrical, Electronic, and Control Engineering from Kongju National University in 2015, and his master's degree from the same university in 2017. He has completed his doctoral coursework as of now. His primary research interest is in SI/PI/EMI/EMC for high-speed signal products for semiconductors, including semiconductor packages, PCBs, connectors, cables, and test sockets. He is actively engaged in research in this field.
저전력 딥러닝 학습 프로세서 설계 동향
박정우, 교수
- 성균관대학교, 반도체시스템공학부
Abstract
Low-power deep learning training processors have gained significant attention due to the need for efficient and privacy-preserving methods for training personalized models. By keeping the training process on-device, sensitive data does not need to be sent to off-device data centers, reducing the risk of data breaches and preserving individual privacy. In this tutorial, we will categorize the different optimization techniques used in recent publications on low-power deep learning training processors. We will discuss how both hardware and software co-optimization is often employed to achieve energy-efficient and high-performance training. We will give specific examples through two of our works, the first of which introduces an end-to-end DNN training processor utilizing a novel FP8 format tailored for DNN training and co-optimized with the hardware for maximum efficiency. In the next work, we will present our novel low-power numeric, which considers the actual hardware implementation to achieve even greater energy efficiency. By optimizing the numeric representation for the specific hardware architecture, we can reduce the energy consumption of the training process without sacrificing model accuracy.
Prof. Jeongwoo Park received the Ph. D. degree from Seoul National University in 2022. He joined Sungkyunkwan University in 2023, where he is currently an assistant professor. His research focus is on deep learning processors, neuromorphic systems, application-specific accelerators, and digital VLSI. Dr. Park received the Gold Prize in Humantech Papers Award (1st prize in circuit design) in 2021, Best Design Award in ISLPED Demo Contest 2021, and Best Demo Award in AICAS 2022.
인공지능을 활용한 반도체 설계
정재용, 교수
- 인천대학교, 전자공학과
Abstract
The exponential growth of machine learning (ML) field has revolutionized many areas, not limited to computer science. With the advance of ML, reinforcement learning (RL) have also demonstrated tremendous success in many challenging problems in various fields from games to protein folding and matrix multiplication algorithms. Inspired by this success, many researchers in semiconductor engineering have attempted to apply RL to their fields. however, RL suffers from notorious sample inefficiency, which is exaggerated in EDA/Testing because data sampling in EDA/Testing is very expensive due to slow simulations. In this tutorial, we introduce our efforts to address this problem and presents an alternative to RL, namely analytic gradient descent (AGD). Our method calculates analytic gradients of a design objective with respect to continuous and discrete design choices through a neural network learned by a simulation model. Then it performs a gradient descent procedure optimizing the design objective directly. We demonstrate AGD on the well-known gate sizing problem and show that our method can be very close to an industry-leading commercial tool in terms of design quality of result (QoR), while it only takes several person-months in comparison to dedicated efforts of human engineering over decades to develop.
Jaeyong Chung is a Professor in the Department of Electronics Engineering at Incheon National University, Incheon, Korea. He received the B.S. degree in electrical engineering from Yonsei University, Seoul, Korea, in 2006, and the M.S. and Ph.D. degrees in electrical and computer engineering from the Department of Electrical and Computer Engineering, University of Texas, Austin, in 2008 and 2011, respectively. He worked at Strategic CAD Lab (SCL), Intel and IBM T.J. Watson Research Center during the summers of 2008 and 2010, respectively. From 2011 to 2013, he was with the Design Compiler Team at Synopsys, Inc., Mountain View, CA. His current research interests include neuromorphic systems and deep learning.
Prof. Chung was the recipient of best paper award nominations at the International Conference on Computer-Aided Design (ICCAD) in 2009 and the Asia and South Pacific Design Automation Conference(ASPDAC) in 2011. One of his co-authored papers is selected in the Asian Test Symposium (ATS) 20th Anniversary Compendium.
Test-driven new methodology of yield analysis during the whole life cycle of SOC chip
Jeongsu Park
- EDAG Group, Sr.Staff Engineer (이사)
- Synopsys Korea
Abstract
The effective yield analysis is one of key challenges at every stage of mass production for SOC chip. The role of yield analysis is to identify the root cause of yield detractor, more fast and more accurate. In general, it takes a very long time to get the result using traditional yield analysis method. For example, it is a time-consuming job by manual for data collecting and mining, interactive analysis, confirming the failure and containment actions. Each test is involved at each manufacturing step but there are so many challenges about the cost, TAT and QoR even the test result is disconnected in each step. It can make some challenge to get the good result even though we have a huge amount of test data. So, I’ll cover the concept of Life cycle management system for SOC chip and explain it how can be extracted the useful data from the test result, automatically. It will contribute to improve the yield of SOC chip.
Jeongsu Park is a Sr.Staff Engineer (이사) of Silicon Life-cycle Management part at Synopsys Korea.
He has been provided a technical supporting and consulting for the Yield Analysis and Failure Analysis at Synopsys, Korea for over 9 years. His expertise includes from the new analysis methodology of Wafer level Testing (ATE), DFT (Design-For-Testing), DFM (Design-For-Manufacturing) for the yield improvement of Fabless and Foundry companies. Prior to joining the Synopsys, Jeongsu Park worked on process integration and yield analysis for the 20 ~ 65nm Logic process in Samsung S.LSI Foundry biz over 5 years. Notable contributions include the stress engineering, high-k metal gate architecture, and Cu metallization. He had a various experience with Tier 1 fabless customers. He worked on the process development for the CMOS Image Sensor at Dongbu HiTek before joining Samsung over 4 years. Mainly focused on the characterization of vertical photodiode structure with several epitaxial layers and the process integration of photodiode and BEOL process.
